46 research outputs found

    Opportunistic Data Collection and Routing in Segmented Wireless Sensor Networks

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    International audienceIn this paper we address routing in the context of segmented wireless sensor networks in which a mobile entity, known as MULE, may collect data from the different subnetworks and forward it to a sink for processing. The chosen settings are inspired by the potential application of wireless sensor networks for airport surface monitoring. In such an environment, the subnetworks could take advantage of airport service vehicles, buses or even taxiing aircraft to transfer information to the sink (e.g., control tower), without interfering with the regular functioning of the airport. Generally, this kind of communication problem is addressed in the literature considering a single subsink in each subnetwork. We consider in this paper the multiple subsinks case and propose two strategies to decide when and where (to which subsink) sensor nodes should transmit their sensing data. Through a dedicated simulation model we have developed, we assess and compare the performance of both strategies in terms of packet delivery ratio, power consumption and workload balance among subsinks. This paper is an intermediate step in the research of this problem, which evidences the benefit of storing the information on the subsinks and distributing it among them before the arrival of the MULE. Based on results, we provide some information on further works

    Adattamento precoce dell’impianto cocleare in età pediatrica

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    L’impianto cocleare costituisce una valida opportunità per fornire l’accesso alla stimolazione uditiva nei casi di ipoacusia severa o profonda di origine cocleare. E’ stato ampiamente dimostrato che l’impianto cocleare è una soluzione sicura ed efficace e che la precocità nell’attivazione è associata a risultati migliori. E’ importante studiare le variabili e gli aspetti che possono interferire con un adattamento precoce e un adeguato accesso al mondo sonoro: caratteristiche del bambino, alleanza terapeutica con la famiglia, aspetti tecnici, medici e organizzativi. Obiettivo di questo lavoro è quello di proporre raccomandazioni utili per gli aspetti organizzativi-pratici relativi alle attivazioni precoci di impianto cocleare, attraverso un particolare modello di analisi SWOT e TOWS

    Comparative Effectiveness of Adalimumab vs Tofacitinib in Patients With Rheumatoid Arthritis in Australia

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    Importance: There is a need for observational studies to supplement evidence from clinical trials, and the target trial emulation (TTE) framework can help avoid biases that can be introduced when treatments are compared crudely using observational data by applying design principles for randomized clinical trials. Adalimumab (ADA) and tofacitinib (TOF) were shown to be equivalent in patients with rheumatoid arthritis (RA) in a randomized clinical trial, but to our knowledge, these drugs have not been compared head-to-head using routinely collected clinical data and the TTE framework. Objective: To emulate a randomized clinical trial comparing ADA vs TOF in patients with RA who were new users of a biologic or targeted synthetic disease-modifying antirheumatic drug (b/tsDMARD). Design, Setting, and Participants: This comparative effectiveness study emulating a randomized clinical trial of ADA vs TOF included Australian adults aged 18 years or older with RA in the Optimising Patient Outcomes in Australian Rheumatology (OPAL) data set. Patients were included if they initiated ADA or TOF between October 1, 2015, and April 1, 2021; were new b/tsDMARD users; and had at least 1 component of the disease activity score in 28 joints using C-reactive protein (DAS28-CRP) recorded at baseline or during follow-up. Intervention: Treatment with either ADA (40 mg every 14 days) or TOF (10 mg daily). Main Outcomes and Measures: The main outcome was the estimated average treatment effect, defined as the difference in mean DAS28-CRP among patients receiving TOF compared with those receiving ADA at 3 and 9 months after initiating treatment. Missing DAS28-CRP data were multiply imputed. Stable balancing weights were used to account for nonrandomized treatment assignment. Results: A total of 842 patients were identified, including 569 treated with ADA (387 [68.0%] female; median age, 56 years [IQR, 47-66 years]) and 273 treated with TOF (201 [73.6%] female; median age, 59 years [IQR, 51-68 years]). After applying stable balancing weights, mean DAS28-CRP in the ADA group was 5.3 (95% CI, 5.2-5.4) at baseline, 2.6 (95% CI, 2.5-2.7) at 3 months, and 2.3 (95% CI, 2.2-2.4) at 9 months; in the TOF group, it was 5.3 (95% CI, 5.2-5.4) at baseline, 2.4 (95% CI, 2.2-2.5) at 3 months, and 2.3 (95% CI, 2.1-2.4) at 9 months. The estimated average treatment effect was -0.2 (95% CI, -0.4 to -0.03; P = .02) at 3 months and -0.03 (95% CI, -0.2 to 0.1; P = .60) at 9 months. Conclusions and Relevance: In this study, there was a modest but statistically significant reduction in DAS28-CRP at 3 months for patients receiving TOF compared with those receiving ADA and no difference between treatment groups at 9 months. Three months of treatment with either drug led to clinically relevant average reductions in mean DAS28-CRP, consistent with remission

    A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

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    The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

    A Prototype of a New Generation Readout ASIC in 65 nm CMOS for Pixel Detectors at HL-LHC

    Get PDF
    The foreseen High-Luminosity upgrade at the CERN Large Hadron Collider (LHC) will constitute a new frontier for particle physics after year 2024, demanding for the installation of new silicon pixel detectors able to withstand unprecedented track densities and radiation levels in the inner tracking systems of current general-purpose experiments. This paper describes the implementation of a new-generation pixel chip demonstrator using a commercial 65 nm CMOS technology and targeting HL-LHC specifications. It was designed as part of the Italian INFN CHIPIX65 project and in close synergy with the international CERN RD53 collaboration on 65 nm CMOS. The prototype is composed of a matrix of 64×64 pixels with 50 μm × 50 μm cells featuring a compact design, low-noise and low-power performance. The pixel array integrates two different analogue front-end architectures working in parallel, one with asynchronous and one with synchronous hit discriminators. Common characteristics are a compact layout able to fit into half the pixel size, low-noise performance (ENC < 100 e− RMS for 50 fF input capacitance), below 5 μW/pixel power consumption, linear charge measurements up to 30 ke− input charge using Time-over-Threshold (ToT) encoding and leakage current compensation up to 50 nA per pixel. A novel region-based digital architecture has been designed in order to ensure > 99% efficiency for expected 3 GHz/cm2 hit rate, 1 MHz trigger rate and 12.5 μs trigger latency at HL-LHC. Pixels have been organized into regions of 4×4 cells and a common synthesized logic shared among all pixels provides a centralized memory for latency buffering, performs the trigger matching and handles the local configuration. The simulated particle inefficiency for this architecture is below 0.1% under nominal HL-LHC conditions. All global biases and voltages required by analogue front-ends are generated on-chip using 10-bit programmable DACs. Bias currents and voltages can be monitored by a 12-bit ADC. A bandgap voltage reference circuit provides a stable reference voltage for all these blocks. The readout of triggered data is based on replicated FIFOs placed at the chip periphery. Data are finally sent off-chip with 8b/10b encoding using a high-speed serializer. Triggerless and debug operating modes are also supported. Chip configuration and slow-control are performed through fully-duplex synchronous Serial Peripheral Interface (SPI) master/slave transactions. The I/O interface uses custom-designed JEDEC-compliant SLVS transmitters and receivers. All blocks and analogue front-ends have been silicon-proven during a previous prototyping phase and were demonstrated to be radiation tolerant up to 580 Mrad Total Ionizing Dose (TID) or beyond. The CHIPIX65 demonstrator was submitted for fabrication on July 2016. It was received back from the foundry on October 2016 and preliminary experimental characterizations started

    Identifying the unmet information and support needs of women with autoimmune rheumatic diseases during pregnancy planning, pregnancy and early parenting: mixed-methods study

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    Background Autoimmune rheumatic diseases (ARDs) such as inflammatory arthritis and Lupus, and many of the treatments for these diseases, can have a detrimental impact on fertility and pregnancy outcomes. Disease activity and organ damage as a result of ARDs can affect maternal and foetal outcomes. The safety and acceptability of hormonal contraceptives can also be affected. The objective of this study was to identify the information and support needs of women with ARDs during pregnancy planning, pregnancy and early parenting. Methods This mixed methods study included a cross-sectional online survey and qualitative narrative interviews. The survey was completed by 128 women, aged 18–49 in the United Kingdom with an ARD who were thinking of getting pregnant in the next five years, who were pregnant, or had young children (< 5 years old). The survey assessed quality-of-life and information needs (Arthritis Impact Measurement Scale Short Form and Educational Needs Assessment Tool), support received, what women found challenging, what was helpful, and support women would have liked. From the survey participants, a maximum variation sample of 22 women were purposively recruited for qualitative interviews. Interviews used a person-centered participatory approach facilitated by visual methods, which enabled participants to reflect on their experiences. Interviews were also carried out with seven health professionals purposively sampled from primary care, secondary care, maternity, and health visiting services. Results Survey findings indicated an unmet need for information in this population (ENAT total mean 104.85, SD 30.18). Women at the pre-conception stage reported higher needs for information on pregnancy planning, fertility, giving birth, and breastfeeding, whereas those who had children already expressed a higher need for information on pain and mobility. The need for high quality information, and more holistic, multi-disciplinary, collaborative, and integrated care consistently emerged as themes in the survey open text responses and interviews with women and health professionals. Conclusions There is an urgent need to develop and evaluate interventions to better inform, support and empower women of reproductive age who have ARDs as they navigate the complex challenges that they face during pregnancy planning, pregnancy and early parenting

    A systematic review of interventions to improve knowledge and self-management skills concerning contraception, pregnancy and breastfeeding in people with rheumatoid arthritis

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    This systematic review aimed to determine the effectiveness of interventions for improving knowledge and/or self-management skills concerning contraception, pregnancy and breastfeeding in people with rheumatoid arthritis (RA). We searched four databases (MEDLINE, CINAHL, Cochrane Trials, PsycINFO) using a comprehensive search strategy. Studies were eligible if they were prospective, published in English from 2004 to 2015, included participants with RA and tested an intervention designed to improve knowledge and/or self-management skills relating to family planning, pregnancy or breastfeeding. As no studies met the latter criterion, the search strategy was expanded to include all prospective studies evaluating RA educational and/or self-management interventions. Data on study characteristics, participant characteristics and programme content were extracted to summarise the evidence base for interventions to support people with RA during their reproductive years. Expanded literature searches identified 2290 papers, of which 68 were eligible. Of these, nine papers (13 %) specifically excluded pregnant women/breastfeeding mothers or recruited only older people.Only one study (1 %) explicitly evaluated pregnancy-focused education via a motherhood decision aid, while eight studies (12 %) incorporated relevant (albeit minor) components within broader RA educational or self-management interventions. Of these, three studies provided methotrexate education in relation to conception/pregnancy/breastfeeding; three incorporated discussions on RA and relationships, impact of RA on the family or sexual advice; one provided information regarding contraception and fertility; and one issued a warning regarding use of biologic therapy in pregnancy/breastfeeding. In conclusion, information regarding family planning, pregnancy or breastfeeding represents a negligible part of published RA educational interventions, with scope to develop targeted resources

    Results from CHIPIX-FE0, a Small-Scale Prototype of a New Generation Pixel Readout ASIC in 65 nm CMOS for HL-LHC

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    A prototype of a new-generation readout ASIC targeting High-Luminosity (HL) LHC pixel detector upgrades has been designed and fabricated as part of the Italian INFN CHIPIX65 project using a commercial 65 nm CMOS technology. This demonstrator, hereinafter referred to as CHIPIX-FE0, is composed of a matrix of 64 7 64 pixels with 50 \ub5m 7 50 \ub5m pixel size embedding two different architectures of analog front-ends working in parallel. The final layout of the chip was submitted and accepted for fabrication on July 2016. Chips were received back from the foundry on October 2016 and successfully characterized before irradiation. Several irradiation campaigns with X-rays have been accomplished during 2017 at Padova INFN and CERN EP/ESE facilities under different uniformity and temperature conditions up to 630 Mrad Total Ionizing Dose (TID). These studies corfirmed negligible degradation of analog front-ends performance after irradiation. First sample chips have been also bump-bonded to 50 \ub5m 7 50 \ub5m and single readout electrode 25 \ub5m 7 100 \ub5m 3D sensors provided by Trento FBK. This represented a major milestone for the entire CHIPIX65 project, offering to the pixel community the first example of a complete readout chip in 65 nm CMOS technology coupled to such a kind of silicon detectors. Extensive characterizations with laser and radioactive sources have started. This paper briefly summarizes most important pre- and post-irradiation results, along with preliminary results obtained from chips bump-bonded to 3D sensors. Selected components of the CHIPIX65 demonstrator have been finally integrated into the large-scale RD53A prototype submitted at the end of summer 2017 by the CERN RD53 international collaboration on 65 nm CMOS technology

    Design of analog front-ends for the RD53 demonstrator chip

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    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment
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